<counter_setname="L2C-310_cnt"count="2"/><categoryname="L2C-310"counter_set="L2C-310_cnt"per_cpu="no"><eventevent="0x1"title="L2 Cache"name="CastOUT"description="Eviction, CastOUT, of a line from the L2 cache"/><eventevent="0x2"title="L2 Cache"name="Data Read Hit"description="Data read hit in the L2 cache"/><eventevent="0x3"title="L2 Cache"name="Data Read Request"description="Data read lookup to the L2 cache. Subsequently results in a hit or miss"/><eventevent="0x4"title="L2 Cache"name="Data Write Hit"description="Data write hit in the L2 cache"/><eventevent="0x5"title="L2 Cache"name="Data Write Request"description="Data write lookup to the L2 cache. Subsequently results in a hit or miss"/><eventevent="0x6"title="L2 Cache"name="Data Write-Through Request"description="Data write lookup to the L2 cache with Write-Through attribute. Subsequently results in a hit or miss"/><eventevent="0x7"title="L2 Cache"name="Instruction Read Hit"description="Instruction read hit in the L2 cache"/><eventevent="0x8"title="L2 Cache"name="Instruction Read Request"description="Instruction read lookup to the L2 cache. Subsequently results in a hit or miss"/><eventevent="0x9"title="L2 Cache"name="Write Allocate Miss"description="Allocation into the L2 cache caused by a write, with Write-Allocate attribute, miss"/><eventevent="0xa"title="L2 Cache"name="Internal Prefetch Allocate"description="Allocation of a prefetch generated by L2C-310 into the L2 cache"/><eventevent="0xb"title="L2 Cache"name="Prefitch Hit"description="Prefetch hint hits in the L2 cache"/><eventevent="0xc"title="L2 Cache"name="Prefitch Allocate"description="Prefetch hint allocated into the L2 cache"/><eventevent="0xd"title="L2 Cache"name="Speculative Read Received"description="Speculative read received"/><eventevent="0xe"title="L2 Cache"name="Speculative Read Confirmed"description="Speculative read confirmed"/><eventevent="0xf"title="L2 Cache"name="Prefetch Hint Received"description="Prefetch hint received"/></category>